Fast FPGA-based pipelined digit-serial/parallel multipliers

摘要

Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. J. Valls, T. Sansaloni,M. M. Peiró, and E. Boemo, "Fast FPGA-based pipelined digit-serial/parallel multipliers", in Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, 1999, p. 482-485